Digital clock manager

A digital clock manager (DCM) is an electronic component available on some field-programmable gate arrays (FPGAs) (notably ones produced by Xilinx). A digital clock manager is useful for manipulating clock signals inside the FPGA, and to avoid clock skew which would introduce errors in the circuit.


Digital clock managers have the following applications:[1]

  • Multiplying or dividing an incoming clock (which can come from outside the FPGA or from a Digital Frequency Synthesizer [DFS][citation needed]).
  • Making sure the clock has a steady duty cycle.
  • Adding a phase shift with the additional use of a delay-locked loop.
  • Eliminating clock skew within an FPGA design.

See also


  1. ^ "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" (PDF). 070804 xilinx.com

This page was last updated at 2019-11-11 00:46, update this pageView original page

All information on this site, including but not limited to text, pictures, etc., are reproduced on Wikipedia (wikipedia.org), following the . Creative Commons Attribution-ShareAlike License


If the math, chemistry, physics and other formulas on this page are not displayed correctly, please useFirefox or Safari